Development in the semiconductor industry is currently in the direction of wafer bonding processes becoming increasingly important. Thus for example novel functions such as motion sensors and/or orientation sensors in cell phones and other portable devices such as game consoles are leading to a rapidly increasing demand for microelectromechanical (MEMS) components which can detect acceleration and rotational speeds.
Another field with rapid growth is components which are produced as so-called 3D ICs. They include a chip system which consists of several layers with transistors (“active layers”) which are connected among one another by means of contacts which lead through the silicon. These plated-through holes are called “through silicon vias” or abbreviated “TSVs” in the industry.
In order to produce these TSVs as economically as possible, as well as to be able to implement other desired advantages such as a small overall packing size, it is necessary to thin the wafers to a suitable size before or after the TSV production or in the course of TSV production. Accordingly it is now distinguished between so-called via first, via middle and via last processes. With respect to thinning of the wafers, it has been found that the desired target thicknesses are no longer sufficient to be able to reliably move the wafer from one process step to the next since the mechanical stability of the wafer, especially in the currently conventional 300 mm wafer, is no longer extant.
Wafers are therefore advantageously temporarily mounted on a carrier so that reliable handling of the thin wafer, which conventionally has a thickness <150 μm, but usually <100 μm and often <80 or even <50 μm, is ensured. After completing the necessary process steps the wafer s again detached from the carrier. These two methods are called temporary bonding and debonding.
In a first process step, the product wafer is bonded onto the carrier by means of suitable bonding technology which is known to one skilled in the art. This bonding step generally takes place such that the first main surface of the product wafer on which the chip structures are built up is oriented such that this surface comes into contact with the temporary adhesive and this adhesive layer subsequently produces the contact with the carrier wafer.
In almost all cases, within the framework of this rear side processing however mechanical thinning of the product wafer takes place. This includes especially grinding steps in which a defined thickness of the product wafer is removed by grinding. Conventionally, in this connection individual grinding steps with different grinding rates and/or grain sizes of the grinding wheels are used. Generally there are a first grinding step with a higher material removal rate (coarse grinding) and a second grinding step with a lower material removal rate (fine grinding).
In order to ensure the quality of the final chips and the integrity of the temporarily bonded wafer in conjunction with the rear side process steps, it is necessary for the temporary adhesive connection to satisfy certain quality criteria. In this connection, there are a host of requirements for the adhesive material which are known to one skilled in the art. They relate among others to the capacity of the adhesive to be able to tolerate certain process conditions which can arise during rear side processing. They include among others temperature stability, compatibility with a vacuum environment (no outgassing), stability of the adhesive relative to chemicals such as solvents, acids, and bases, compatibility with diverse mechanical loads or electromagnetic waves (for example irradiation with light of a certain wavelength) and various combinations of these parameters. In addition to the demands on the adhesive material, there is also a host of parameters which relate to the geometrical and mechanical integrity of the adhesive layer. In particular it is of enormous importance for the success of rear side processing that the adhesive layer has a precisely defined and reproducible thickness, and no voids.
In contrast to thinning of an individual wafer however in the case of a temporarily bonded wafer the carrier wafer and the adhesive layer are located between the wafer support and the grinding means (grinding wheel, etc.). Thus the thickness of the carrier wafer and the adhesive layer together influences the uniformity of the final thinned product wafer.
Therefore, it can be stated in summary that it is necessary to be able to precisely control and monitor the uniformity of the thickness of the adhesive layer and generally also the absolute thickness value in a production process. For certain cases, depending on the control of the grinding process it can also be necessary to know the thickness of the carrier wafer—under certain circumstances also that of the entire temporarily bonded stack. In any case, it is, however, necessary to ensure a corresponding quality of the adhesive layer with respect to the uniformity of the thickness and optionally the absolute thickness value.
With respect to the voids, it holds that during a grinding process and possible subsequent polishing process they would lead to the wafer being inadequately mechanically supported, and in this way damage of the wafer or at least nonuniformities of the wafer thickness which is desired during thinning can occur. This nonuniformity is caused by the mechanical flexibility of the base which is formed by these voids. In other words, the wafer would for example bend/sag into these voids during grinding and thus less substantial removal would take place at these sites; this would subsequently result in a locally elevated thickness of the thinned wafer. This effect would be stronger, as the target thickness of the thinned wafer becomes smaller since it becomes more flexible with decreasing thickness. Ultimately this can even lead to fracture of the wafer during thinning. These fracture events constitute a major risk for grinding and/or polishing processes since the resulting relatively large material pieces can entail further damage to the entire wafer, but also of the grinding wheels and/or the polishing device. Aside from these problems, during grinding and/or polishing these voids can also lead to faults during the remaining rear side process steps. It should be noted here only as an example that gases enclosed in these voids during process steps which occur in vacuum chambers can lead to the thinned silicon wafers bursting during these process steps at these sites. In addition to the loss of the chip located at this site this would also result in further problems since the resulting particles would contaminate the system used in which the bursting took place, and under certain circumstances other production units and possibly would also entail quality problems on other wafers which have been processed on this unit.